In order to enhance the performance and capacity of a single semiconductor package to be suitably used in a miniaturized high-speed electronic product, Multichip Module incorporating two or more semiconductor chips into a single package has been developed, which desirably has a reduced size and improved electrical functionality. The multichip module is further advantageous of minimizing a limitation of the system operation speed and shortening a transmission path between the semiconductor chips to thereby reduce signal delay and access time.
A common structure of multichip module employs side-by-side arrangement having the two or more chips mounted side-by-side on a surface of a substrate. However, as the area of the substrate must be increased when the number of chips is increased, the side-by-side arrangement is undesirably cost-ineffective to implement.
Accordingly, a method of stacking the chips has been proposed, and the stacking arrangement of chips can vary with the design of chips and the way of performing a wire-bonding process. For example, when using chips each having bond pads disposed at one side thereof, such as flash memory chips, the chips should be stacked in a step-like manner as to expose the side having the bond pads of each of the chips such that the wire-bonding process can subsequently be performed on the chips.
Referring to FIG. 1, a multichip stacking structure disclosed by U.S. Pat. No. 6,900,528 is formed by stacking a plurality of chips on a chip carrier 10. A first chip 11 is mounted on the chip carrier 10, and a second chip 12 is stacked on the first chip 11 without covering bond pads 110 of the first chip 11; similarly, a third chip 13 is stacked on the second chip 12 without covering bond pads 120 of the second chip 12, such that a step-like multichip stacking structure is formed and the wire-bonding process can be performed to electrically connect the first, second and third chips 11, 12, 13 to the chip carrier 10 via a plurality of bonding wires 14. The step-like stacking arrangement advantageously does not interfere with the wire-bonding process performed on the bond pads 110, 120 of the first and second chips 11, 12.
The foregoing step-like multichip stacking structure can save more space on the chip carrier as compared to the side-by-side multichip mounting arrangement. The step-like multichip stacking structure is further advantageous of accelerating the fabrication processes by performing the wire-bonding process in one stage after all the chips are stacked on the chip carrier and forming an encapsulant for encapsulating the stacked chips and bonding wires through a molding process. However, due to the provision of bonding wires, a mold gate G in the molding process must be made to allow a mold flow of an encapsulating resin injected through the mold gate G to have a direction parallel with the bonding wires, for example as shown in FIG. 2A or 2B. In FIG. 2A, the mold gate G is located relatively distant from the bonding wires, and in FIG. 2B, the mold gate G is located relatively close to the bonding wires.
However, as shown in the FIG. 2A, with the mold gate G being located relatively distant from the bonding wires, the encapsulating resin, which is injected through the mold gate G to form the encapsulant for encapsulating the stacked chips on the chip carrier, would provide direct impact on the overlying chip and easily makes the overlying chip delaminated from the underlying chip (as indicated by dotted lines).
On the other hand, as shown in FIG. 2B, during the molding process where the mold gate G is located relatively close to the bonding wires, the encapsulating resin injected through the mold gate G may easily have voids formed at positions corresponding to suspended portions of the stacked chips due to backflow of the encapsulating resin, thereby leading to a popcorn effect in subsequent thermal cycle and reliability test and degrading the quality of the package product.
Therefore, the problem to be solved here is to provide a multichip stacking structure, which can eliminate the problems of void formation and chip delamination during the molding process.